1. Field of the Invention
The present invention relates to an improvement in an input stage of a semiconductor integrated circuit apparatus employing emitter-coupled logic (hereinafter referred to as ECL).
2. Description of the Background Art
FIG. 1 is a circuit diagram showing a conventional ECL circuit. A buffer circuit 1 is formed by a transistor Q.sub.1 and a constant current source circuit 2. The transistor Q.sub.1 is an emitter follower buffer NPN transistor. The transistor Q.sub.1 has a base connected to an input terminal 3, a collector connected to a first power supply line 4 and an emitter connected to the constant current source circuit 2. The transistor Q.sub.1 derives a signal which is responsive to an input signal received in the input terminal 3 at its emitter. The constant current source circuit 2 is a constant current load for supplying constant current to the transistor Q.sub.1. The constant current source circuit 2 is formed by a transistor Q.sub.2 and a resistor R.sub.1. The transistor Q.sub.2 is an NPN transistor, which has a base connected to a reference voltage input terminal 5, a collector connected to the emitter of the transistor Q.sub.1 and an emitter connected to a second power supply line 6 through the resistor R.sub.1.
An ECL differential pair 7 is formed by transistors Q.sub.3 and Q.sub.4. The transistors Q.sub.3 and Q.sub.4 are prepared by NPN transistors, emitters of which are commonly connected with each other. The transistor Q.sub.3 has a base connected to the emitter of the transistor Q.sub.1 and a collector connected to the first power supply line 4 through the resistor R.sub.2 as well as to an output terminal 8. The transistor Q.sub.4 has a base connected to a logic comparison reference voltage input terminal 9 and a collector connected to the first power supply line 4. The logic comparison reference voltage input terminal 9 is set at a potential value evaluated by adding the base-to-emitter potential of the transistor Q.sub.1 to an intermediate potential between a high-level signal and a low-level signal supplied to the input terminal 3. The transistor Q.sub.3 is made conductive/nonconductive depending on whether or not a signal level supplied to its base is higher than the potential of the logic comparison reference voltage input terminal 9, so that a high-level or low-level signal is outputted from the output terminal 8.
A constant current source circuit 10 is adapted to supply constant current to the ECL differential pair 7, and is formed by a transistor Q.sub.5 and a resistor R.sub.3. The transistor Q.sub.5 is prepared by an NPN transistor, which has a base connected to the base of the transistor Q.sub.2, a collector connected to the emitter common junction of the transistors Q.sub.3 and Q.sub.4 and an emitter connected to the second power supply line 6 through a resistor R.sub.7.
Operation of the circuit in the aforementioned structure will now be described. When the input terminal 3 receives a high-level signal, the transistor Q.sub.3 of the ECL differential pair 7 is supplied in its base with a high-level signal which is higher than the potential at the logic comparison reference voltage input terminal 9 through the buffer transistor Q.sub.1, whereby the transistor Q.sub.3 enters a conducting state and the transistor Q.sub.4 enters a nonconducting state. Current flows to the resistor R.sub.2 to cause voltage drop, and hence a low-level signal is outputted from the output terminal 8.
When the input terminal 3 receives a low-level signal, on the other hand, the transistor Q.sub.3 of the ECL differential pair 7 is supplied in its base with a low-level signal which is lower than the potential at the logic comparison reference voltage input terminal 9 through the buffer transistor Q.sub.1, whereby the transistor Q.sub.3 enters a nonconducting state and the transistor Q.sub.4 enters a conducting state. Since no current flows to the resistor R.sub.2 to cause no voltage drop in this case, a high-level signal is outputted from the output terminal 8.
As hereinabove described, the transistor Q.sub.1 is regularly in a conducting state when a high-level or low-level signal is received in the input terminal 3, to level-shift the potential of the high-level or low-level signal by its base-to-emitter voltage to derive the same at the emitter. In such a normal operation state, current to the constant current source circuit 2 is supplied from the first power supply line 4. Assuming that the constant current supplied to the constant current source circuit 2 is represented by I.sub.0 and the grounded emitter current amplification factor of the transistor Q.sub.2 is 100, current of I.sub.0 /100 is supplied to the base of the transistor Q.sub.2 from a reference circuit (not shown).
FIG. 2 is a circuit diagram showing another conventional ECL circuit, wherein the constant current source circuit 2 shown in FIG. 1 is formed by a current mirror circuit. The constant current source circuit 2 comprises a transistor Q.sub.2, a resistor R.sub.3 and a diode D.sub.1. The diode D.sub.1 is equivalent to a transistor whose base and collector are interconnected with each other. The transistor Q.sub.2 has a base connected to a reference voltage input terminal 5 through the resistor R.sub.3 as well as to a second power supply line 6 through the diode D.sub.1 and an emitter connected to the second power supply line 6. This structure is so designed that a reference circuit (not shown), which is connected to the reference voltage input terminal 5, has reference voltage of V.sub.REF and supplies reference current of I.sub.01 {I.sub.01 =(V.sub.REF -V.sub.F(D1) /R.sub.3 }. V.sub.F(D1) shows a voltage drop of diode D.sub.1.
In the conventional semiconductor integrated circuit device having the aforementioned structure, the transistor Q.sub.1 enters a nonconducting state when the input terminal 3 is opened, whereby the constant current I.sub.0 to the constant current source circuit 2 cannot be supplied from the first power supply line 4. Thus, no collector current flows in the transistor Q.sub.2. Therefore, the transistor Q.sub.2 operates as a diode formed by the base and the emitter. Thus, load current of the reference circuit, which is base current of the transistor Q.sub.2 in the circuit shown in FIG. 1, is increased from I.sub.0 /100 to I.sub.0, whereby output voltage of the reference circuit is changed. In the circuit shown in FIG. 2, on the other hand, the current I.sub.01 flowing in the diode D.sub.1 is divided by the diode D.sub.1 and the transistor Q.sub.2, to cause change in the anode potential of the diode D.sub.1, which is reference voltage of the constant current circuit 10. Consequently, all of the constant current sources receiving these reference voltages are changed in current value, to cause deviation in potential of an internal circuit when the semiconductor integrated circuit device is used under the condition that the input terminal 3 is opened.